Integrated Circuit Designer - Layout at Asteralabs

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products. Key Job Duties: • The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS] • The management of manufacturing process of the products, including technology yield and performance of the products. • The development of test programmes and procedures to ensure the products meet their performance specifications. • The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment. Basic Qualifications: • At least a bachelor’s degree in electrical engineering Required Experience: • 4+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology. • Experience with layout extraction tools and to analyzing layout parasitic to achieve high quality layout for highspeed circuits. • EMIR and antenna DRC rules aware layout practices. • Experience writing SKILL and TCL scripts is highly recommended We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.