Digital - ASIC Design Automation Engineer at Eliyan

Join the leading chiplet startup! As an Eliyan digital designer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing micro-architecture specifications and RTL design descriptions for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. MUST BE WILLING TO WORK ONSITE - M-F KEY RESPONSIBILITIES Flow Automation and Quality Gates • Own and define the front-end release methodology, including release criteria, handoff checkpoints, and cross-team gating procedures • Build and maintain Jenkins-based CI for Lint, CDC, RDC, and static timing analysis across active design projects, with automated dashboards and per-project triage workflows • Integrate quality gates into the RTL handoff process: elaboration checks, SDC review, CSR spec consistency, and coding guideline enforcement • Standardize waiver management workflows across lint and CDC tools; close vendor AE feedback loops AI-Augmented Tooling and Documentation • Implement automated spec-to-RTL consistency checking using LLM-driven diff and review pipelines • Build documentation generation infrastructure (version-controlled, CI-integrated) and prototype LLM-driven RTL review tooling • Evaluate and integrate new AI/LLM tooling into the design flow; benchmark output quality and establish guardrails for team-wide rollout Design Training Track • Ramp on CDC fundamentals, shared library design, MCU/SoC integration, and lint methodology under dedicated senior mentorship • Contribute to RTL development on shared library and CDC-adjacent blocks as readiness builds, with a structured path to digital design ownership over 18-24 months and quarterly readiness reviews • MINIMUM QUALIFICATIONS • BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field • Demonstrated ability to acquire new technical domains rapidly, evidenced by coursework, projects, internships, research, or open-source contributions • Proficiency in Python, Tcl, shell scripting, Git, and Linux; working familiarity with Makefiles and CI/CD systems (Jenkins, GitHub Actions, GitLab CI, or equivalent) • Foundational understanding of digital logic design, SystemVerilog or other HDLs, and computer architecture • Strong written and verbal communication, with the ability to produce technical documentation that enables team-wide adoption • Self-directed problem-solving disposition and comfort operating in a fast-paced, evolving environment • Authorized to work in the United States; sponsorship may be considered for exceptional candidates PREFERRED QUALIFICATIONS • 3+ years of relevant industry experience • Hands-on experience with LLM/AI tooling and agent frameworks (Anthropic Claude, OpenAI, or equivalent) • Familiarity with industry-standard EDA tools (Synopsys VCS, Verdi, PrimeTime, Design Compiler, Fusion Compiler; Cadence Genus; Spyglass; Questa; JasperGold) • Background in machine learning or data engineering, including production model development or pipeline construction • Embedded systems or microcontroller firmware experience (ARM Cortex-M class or similar) • Coursework or project exposure to digital design, SoC, PHY, SerDes, or chiplet interconnect domains • Open-source contributions to design automation, hardware verification, or developer tooling