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ExecutiveFull-timeAI
Salary Range
$142,800 - $193,200 /year
This salary is estimated based on similar roles. The actual salary may vary.
About the Role
We are looking for a Head of Design Verification to own and scale verification for all major interface IP subsystems across Etched silicon. This is a hands-on technical leadership role that involves managing a small team while personally owning DV strategy, execution, and tape-out sign-off for critical subsystems.
Key Responsibilities
- →Own end-to-end DV strategy and sign-off for Interface IP across Etched SoCs
- →Act as the technical authority on correctness, protocol compliance, performance, and robustness
- →Lead DV for CPU subsystems and high-speed interfaces
- →Architect and evolve SystemVerilog/UVM verification environments
- →Drive vendor IP integration and verification gap closure
- →Partner closely with architecture, RTL, SoC DV, and software teams
- →Hire, mentor, and lead a small Interface IP DV team
- →Advise on emulation testing for pre-silicon validation
Requirements
- ✓10+ years of design verification experience with ownership of complex IP or SoC subsystems
- ✓Deep hands-on expertise in SystemVerilog and UVM
- ✓Strong understanding of SoC mCPU design and high-speed interfaces
- ✓Tape-out experience with final DV sign-off responsibility
- ✓Systems-level DV mindset
- ✓Comfortable being hands-on in a fast-moving startup environment
