Principal Engineer, Analog Design at RenesasElectronics

Individual Contributor role for Technical leader with 15+ years of experience in Analog and Power IC development within 2.6B$ Power Business Unit at Renesas. Primary responsibilities include leading the design and development of power management ICs, including voltage regulators, power converters, and other related components and collaborate with cross-functional teams to ensure successful integration of ICs into larger systems. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas’s massive Power product portfolio. In the Technical leader role, candidate will be directly responsible for end-to-end IC design (from specifications to PRA). Will be expected to work with other team members to do successful Chips along with mentoring the junior members. This is an IC role with complete focus on product development and no people management. Essential Functions: • Must have led and should be experienced of developing multiple Power ICs with Switching Converters, starting from system level specifications and taking ICs to production. • Identify and resolve technical challenges and risks. Provide technical expertise and mentorship to junior engineers. Able to lead group of Engineers and navigate through all stages of IC development while handling and mitigating challenges, ensuring high quality silicon while adhering to the schedules based on business needs. • Must be proficient in designing complete switching converters and all involved I/Ps. Should be fully aware of all challenges pertaining to high current/power switching converters design including Noise, Power dissipation etc and their mitigation. • Should have a very good understanding of Power devices, operations and design trade-offs for better performance & reliability. • Should be able to lead and guide development, integration of complex I/Ps like +ve/-ve Charge Pumps, Source-Sink LDOs, Ultra-low power Oscillators (including Relaxation type), Temperature Sensor, Current Sense, SAR ADCs, House Keeping blocks, Protection (Thermal, Under-Voltage, Over-Voltage, Over Current etc) and other analog blocks including Bandgap references, V2I, Analog Buffers, Op-Amps, Comparators, High speed level shifters etc. Thorough understanding of Switch Cap circuits is a must. • Must have in-depth understanding of and should be able to choose, design & compensate Control loops keeping in mind the target performance. • Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. • Should be able to architect the IC and break down System/Chip-top level requirements into block level specifications and then work with Team members and develop the blocks, integrate the blocks into Top level and ensure desired performance. • Must have good understanding of commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each. • Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance. • Should have in-depth knowledge of Analog layouts, FET layouts, Noise isolation techniques and be able to guide the layout development from floor planning till Chip Top completion and verification and do trade-offs based on desired performance. • Must be conversant with the standard design, extraction and simulation flows & tools, speed, convergence, accuracy trade-offs and should be able to optimize setups based on Pre/Post (with/without) Parasitic using simulator options, debug and navigate through tool related challenges. • Should be able to setup design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. • Should be able to mentor Freshers and Junior engineers for upscaling their technical skills as well as other skills needed for better efficacy. • Should have in-depth understanding of ESD, LU and other IC level issues and be able to define protection for the I/O ring for the IC