Principal Test Engineer/DFT Architect at RenesasElectronics

Test and DFT Architecture · Define product-level test and DFT strategy, including wafer probe, final test, characterization, qualification, GRR, production test flow, and cost-of-test targets. · Partner with design, systems, validation, product engineering, test engineering, quality, operations, and manufacturing teams to define DFT requirements early in the lifecycle. · Drive requirements for test muxes, scan/debug access, analog observability, digital controllability, embedded monitors, BIST where applicable, trim/calibration access, fuse/NVM test modes, and diagnostic hooks. · Review schematics, architecture documents, specifications, register maps, and test-mode plans to identify testability gaps before design freeze. · Establish reusable DFT and test-access standards for power, analog, mixed-signal, and digitally assisted products. ATE and Production Test Strategy · Define ATE platform strategy, including tester selection, instrument usage, multisite targets, handler/prober compatibility, hardware reuse, test-time optimization, and production scalability. · Establish strategic test flows, binning methodology, screen strategy, guardband approach, data collection strategy, and test naming conventions. · Assess feasibility for critical tests such as high-voltage stress, analog parametric measurements, digital interface testing, trim/calibration, NVM programming, wafer-level characterization, and production diagnostics. · Influence test hardware architecture, including load boards, probe cards, sockets, change kits, and interface circuitry, to improve accuracy, signal integrity, and multisite scalability. · Guide platform-transition strategies and production test readiness for new products and product families. Circuit and Testability Leadership · Apply circuit-level knowledge to ensure key internal nodes, bias conditions, clocks, references, protection circuits, calibration loops, and failure mechanisms are observable and controllable on ATE. · Work with design teams to ensure critical analog, digital, and power-management functions can be accurately measured in production. · Evaluate the impact of circuit architecture, wafer-test strategy, package choice, and test platform capability on test coverage, yield learning, quality risk, cost, and cycle time. · Support complex silicon and production debug by connecting ATE data, bench data, circuit behavior, design intent, process variation, and production yield trends. · Identify testability risks early, including limited test access, insufficient characterization coverage, weak diagnostics, limited traceability, or late test-mode definition. Cross-Functional Influence · Serve as senior technical interface between design, DFT, test engineering, product engineering, validation, quality, operations, and manufacturing partners. · Lead testability reviews at key development gates and ensure issues are resolved before tape-out, qualification, or production release. · Create test architecture documentation, DFT checklists, coverage expectations, production-readiness criteria, and product-family test strategy templates. · Mentor engineers on DFT principles, ATE methodology, debug strategy, and scalable production test development. · Influence roadmap decisions for ATE platforms, test data infrastructure, characterization automation, production analytics, and AI-enabled test optimization. ---