Senior Analog Engineering Manager at RenesasElectronics

                                       Technical Leadership (DDR5 / DDR6) • Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures. • Provide technical oversight for critical analog and mixed-signal blocks, including: • High-speed TX/RX datapaths • Advanced equalization, termination, and training circuits • DLL/PLL-based clocking solutions for multi-GHz operation • Voltage, reference generation, and power-aware IO design • Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates. • Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction. • Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.                                      People & Organization Leadership • Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces. • Set technical direction, performance expectations, and development plans for senior and principal engineers. • Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs. • Foster a culture of technical rigor, ownership, and execution excellence.                                        Program & Cross-Functional Execution • Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk • Partner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, program management, and customers • Interface with foundries, IP vendors, and standards bodies as needed to ensure successful delivery and future readiness.                                    Methodology, Quality & Roadmap • Establish robust design and signoff methodologies for next-generation high-speed PHYs. • Drive continuous improvement in simulation accuracy, mixed-signal verification, and silicon debug efficiency. •  Lead long-term DDR5 sustainment and DDR6 technology roadmap planning, including architectural trade-offs and scaling strategies. • Anticipate challenges from data-rate scaling, power efficiency, and advanced process technologies