Sr Staff Engineer, Compiler at RenesasElectronics

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware. This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications.. 【Job Description】 ・Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration ・Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning) ・Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies ・Partner with SoC and AI accelerator architects to influence hardware features through compiler insights ・Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models ・Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations) ・Mentor senior engineers and set technical direction without people‑management responsibilities 【Impact & Differentiators】 Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards.  An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.