Sr Staff/Staff/Senior Engineer– IP Design Verification at RenesasElectronics

RenesasElectronics

Noida, in·1d ago

SeniorFull-timeGitAIML

Salary Range

$26,520 - $35,880 /year

Estimated

This salary is estimated based on similar roles. The actual salary may vary.

About the Role

We are looking for an experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. This role involves end-to-end verification of complex digital IPs and subsystems, ensuring first-pass silicon success through advanced verification methodologies and AI tools.

Key Responsibilities

→Own end-to-end verification execution for complex digital IPs and subsystems from specification to sign-off
→Define and drive IP-level verification strategies, including test plans, coverage models, and closure criteria
→Develop scalable, reusable UVM-based verification environments for IP and subsystem verification
→Lead functional, code, assertion, and cross-coverage closure, ensuring high-quality sign-off with clear metrics
→Apply AI/ML-assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
→Drive constraint random and directed test methodologies for thorough protocol, corner-case, and stress verification
→Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
→Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
→Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
→Work with EDA vendors to evaluate and adopt next-generation verification, coverage, and analytics tools
→Mentor junior engineers and promote best-in-class verification practices and continuous improvement
→Support Gate-Level Simulation (GLS), low-power verification, and post-silicon debug when required
→Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration

Requirements

✓Extensive experience in end-to-end verification of complex digital IPs and subsystems
✓Strong expertise in UVM-based verification environments
✓Proficiency in AI/ML-assisted verification techniques
✓Experience with SVA, checkers, scoreboards, and protocol monitors
✓Knowledge of EDA tools and next-generation verification methodologies
✓Ability to mentor junior engineers and promote best practices
✓Experience with Gate-Level Simulation, low-power verification, and post-silicon debug