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Principal Engineer, ASIC Development Engineering (Mixed Signal IP Layout) at Sandisk
SandiskBengaluru, KA, inΒ·7h ago
SeniorFull-timeGitAI
Salary Range
$26,520 - $35,880 /year
This salary is estimated based on similar roles. The actual salary may vary.
About the Role
We are seeking a technically proficient Analog/High Speed DDR IO Layout Designer with 8-12 years of experience. The ideal candidate will develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability.
Key Responsibilities
- βDevelop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability.
- βCollaborate with design engineers to understand design requirements and translate them into precise layouts.
- βDebug DRC, ERC, LVS, EMIR, and PERC issues independently.
- βIntegrate custom blocks into the overall chip design with the physical design team.
- βIdentify and resolve layout-related issues, providing creative solutions to meet design specifications.
- βConduct design reviews and provide technical feedback to improve layout practices.
- βStay updated with industry trends, tools, and technologies to enhance layout processes.
Requirements
- β8-12 years of experience in Analog/High Speed DDR IO IC layout design.
- βProficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
- βHands-on experience with custom layout design for Analog and IO circuits, including Bandgap references, LDOs, Clocking circuits, GPIOs, and High speed DDR IOs.
- βFamiliarity with custom digital layout for high speed logic paths.
- βKnowledge of signal integrity issues, including clock/data routes, differential routing, and shielding.
- βStrong understanding of analog/IO design principles, including circuit performance and parasitic effects.
- βAwareness of layout techniques to mitigate ESD and latch-up issues.
- βAdvanced knowledge of CMOS and FinFET technologies and their impact on design and performance in deep sub-micron process nodes, specifically 5nm and below.
- βExperience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
- βExperience with layout optimization for power, performance, and area (PPA) metrics.
- βExcellent problem-solving skills and attention to detail.
- βEffective communication and teamwork abilities.
- βPreferred Skills
- βKnowledge of scripting languages (e.g., Skill, TCL, and SVRF) for automation tasks.
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