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Principal Engineer, ASIC Development Engineering (RTL Design) at Sandisk
SandiskBengaluru, KA, in·1w ago
SeniorFull-timeGit
Salary Range
$26,520 - $35,880 /year
This salary is estimated based on similar roles. The actual salary may vary.
About the Role
We are seeking a highly experienced and motivated Principal Engineer specializing in SoC RTL Design for System-on-Chip (SoC) solutions. This role involves driving the SoC Architecture, Design, and integration of complex digital systems.
Key Responsibilities
- →Define and review SoC architecture and design specifications
- →Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
- →Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
- →Drive cross-functional collaboration with various engineering teams
- →Provide technical leadership and mentorship to engineering teams
- →Drive integration and debug efforts for subsystem and full-chip level
- →Contribute to IP selection, evaluation, and integration in SoC designs
- →Deliver clear project updates to stakeholders
Requirements
- ✓Expertise in Verilog/SystemVerilog for RTL design
- ✓Experience with SoC architecture and complex digital systems
- ✓Knowledge of design methodologies including lint, CDC, RDC and FC-Elab
- ✓Strong technical leadership and mentorship abilities
- ✓Experience with IP selection and integration
- ✓Excellent communication skills for stakeholder updates
