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Principal Engineer, VLSI Design Engineering (SOC Verification, System Verilog, UVM) at Sandisk
SandiskBengaluru, KA, in·3h ago
SeniorFull-timePythonC++Git
Salary Range
$26,520 - $35,880 /year
This salary is estimated based on similar roles. The actual salary may vary.
About the Role
We are looking for a Logic Verification Engineer with 8+ years of experience to join our team. This role involves leading and developing test plans, tests, and verification infrastructure for complex IP/Sub-Systems or SoC.
Key Responsibilities
- →Create verification environment using UVM methodology
- →Create reusable bus functional models, monitors, checkers, and scoreboards
- →Drive functional coverage driven verification closure
- →Work with architects, designers, and post-silicon teams
- →Hands-on contributions to SVA development like coding, porting, and maintaining System Verilog Assertions
- →Development of tools for Design and Verification support
- →Debug failures and root-cause it by interacting with other teams/groups
Requirements
- ✓Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
- ✓Basic knowledge of C, C++, SystemC, Perl, Python, Tcl, Shell is preferable
- ✓Unit/Sub-system/SOC level verification experience
- ✓Experience in leading verification closure of complex IP/SOC for at least one project
- ✓Exposure to industry standard verification tools for simulation and debug
- ✓RTL & Gate Level Simulations
- ✓Proficiency in Verilog, System Verilog and Assertions, UVM and Functional Coverage
- ✓Exposure to Verification Fundamentals
- ✓Verification Automation using scripts like Perl, Shell, Tcl/Tk
- ✓Good debugging and problem solving skills
- ✓Good communication skills and ability, desire to work as a team player
- ✓Exposure to Analog verification will be an additional plus point
- ✓Knowledge on Memory (SRAM/DRAM/ROM/Flash) Circuits/Logic
- ✓Preferred exposure to NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal
- ✓Cadence Schematic and layout environment
