Sr. Analog Frontend Design Automation Engineer at Solidigm

We are seeking a Senior Analog Frontend Design Automation Engineer to accelerate analog and mixed-signal design productivity by building and owning robust, validated simulation and analysis flows and integrating them into a scalable custom CAD environment. This role is hands-on and highly cross-functional, partnering closely with analog designers, AMS verification, reliability, and PDK teams to standardize workflows and improve quality, repeatability, and simulation-to-silicon correlation. The ideal candidate brings strong experience in custom CAD enablement (Virtuoso-based environments), SPICE simulation automation, and reliability/EMIR-aware methodologies, with the ability to translate real designer pain points into practical tools, frameworks, and flow improvements. We are seeking a Senior Analog Frontend Design Automation Engineer to accelerate analog and mixed-signal design productivity by building and owning robust, validated simulation and analysis flows and integrating them into a scalable custom CAD environment. This role is hands-on and highly cross-functional, partnering closely with analog designers, AMS verification, reliability, and PDK teams to standardize workflows and improve quality, repeatability, and simulation-to-silicon correlation. The ideal candidate brings strong experience in custom CAD enablement (Virtuoso-based environments), SPICE simulation automation, and reliability/EMIR-aware methodologies, with the ability to translate real designer pain points into practical tools, frameworks, and flow improvements. Key Responsibilities Simulation & Methodology Enablement • Develop and maintain validated SPICE simulation flows (e.g., HSPICE/Spectre-class), including run templates, corner setups, Monte Carlo sampling schemes, and convergence guidelines. • Create standardized workflows for analog blocks (e.g., sense amplifiers, charge pumps, references, HV switching circuits), enabling repeatable setup and trustworthy results across projects. • Drive simulation-to-silicon correlation by aligning device models, PVT corners, and simulation assumptions to the PDK; identify mismatches and coordinate improvements.Custom CAD / Virtuoso Automation • Build and support custom CAD automation spanning schematic entry, testbench generation, run orchestration, results harvesting, and regression execution, emphasizing reproducibility and ease-of-use. • Develop scripts/tools (Skill/Tcl/Perl/Python or equivalent) to automate repetitive tasks, reduce manual errors, and improve designer throughput. • Provide end-user support and documentation (best practices, templates, debug playbooks) to reduce flow friction and improve adoption.Reliability / EMIR / Extraction-aware Enablement (Frontend Focus) • Enable flows that connect simulation with layout-derived effects—supporting workflows that incorporate parasitics and reliability considerations (e.g., extraction-aware simulation readiness, EM/IR-aware checks, reliability/ERC integration). • Collaborate with layout/verification/reliability partners to improve clarity and consistency of rule interpretation and analysis setup where needed.Cross-Functional Leadership • Partner with analog design, AMS verification, PDK/library teams, and broader DA infrastructure to deliver standardized methodologies and scalable flow deployment. • Contribute to DA standards (methodology, signoff expectations where applicable, and flow QA/regression practices) to reduce late-cycle churn and risk.