Jobs → Design → Design Verification Engineer

Design Verification Engineer

Jagan Y.CanadaSENIORPosted 2h ago
SystemVerilogUVMASIC/SoC VerificationFunctional CoverageVCSXceliumQuestasimAXIPCIeEthernet
About the Role We are actively looking for experienced semiconductor engineering professionals for multiple opportunities in ASIC/SoC engineering. Key Responsibilities • Perform design verification of ASIC/SoC components • Develop and execute verification test plans • Utilize SystemVerilog and UVM methodologies • Debug RTL issues and ensure functional coverage Requirements • 8+ years of experience in ASIC/SoC verification • Strong knowledge of SystemVerilog and UVM • Experience with VCS, Xcelium, and Questasim tools • Familiarity with AXI, PCIe, and Ethernet protocols • Hybrid work for the first month, followed by remote work

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