Jobs → Design → Design Verification Engineer

About the Role We are looking for a Design Verification Engineer with IP DV experience to join our team. This role focuses on verifying IP designs and developing reusable testbenches. Key Responsibilities • Perform design verification using SystemVerilog and UVM • Develop reusable testbenches for IP designs • Work with protocols such as PCIe, Ethernet, AXI/AMBA, ARM/ARC CPU • Ensure functional coverage and verification sign-off • Integrate vendor IP/VIP Requirements • 8+ years of experience in Design Verification • Strong hands-on experience with SystemVerilog and UVM • Experience with IP Design Verification and reusable testbench development • Knowledge of protocols: PCIe, Ethernet, AXI/AMBA, ARM/ARC CPU • Functional coverage, debugging, and verification sign-off experience • Vendor IP/VIP integration experience preferred Note: Candidates must be willing to work onsite in San Jose, CA.