SoC Design Engineer
Priya UpadhyayUnited StatesMIDPosted 12d ago
VerilogSystem VerilogVHDLTclPythonSDCUPFCDCRDCLintingPower AnalysisSynthesis
About the Role
We are seeking an experienced SoC Design Engineer to drive the design and implementation of SoC blocks and subsystems. This role requires strong SoC integration experience and expertise in RTL design, timing, and power optimization.
Key Responsibilities
• Develop architecture specifications for SoC subsystems
• Integrate complex subsystems at the SoC level
• Collaborate with IP providers to determine optimal configurations
• Develop and propagate timing constraints (SDC) and power intent (UPF)
• Establish and maintain CDC, RDC, linting, and power analysis flows
• Analyze PPA (Power, Performance, and Area) reports and recommend improvements
Requirements
• Masters degree in Electrical Engineering or a related field, or equivalent experience
• 4+ years of experience in SoC integration
• Experience integrating complex SoC subsystems, such as processors, PCIe, and DDR
• Knowledge of RTL design using Verilog, System Verilog, or VHDL
• Experience with CDC/RDC, linting, power analysis, and synthesis flows
• Strong scripting and programming skills in Tcl and Python