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LeadFull-timeGitAIML
Salary Range
$76,500 - $103,500 /year
This salary is estimated based on similar roles. The actual salary may vary.
About the Role
We are looking for a SerDes Digital Design Lead to join Eliyan, a leading chiplet startup. This role involves driving the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems.
Key Responsibilities
- →Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling
- →Design and optimize PHY-level digital logic including TX driver control, RX datapath, and PCS sublayers
- →Architect and implement forward error correction (FEC) encoder/decoder blocks
- →Drive RTL design quality through lint, CDC/RDC analysis, and synthesis optimization
- →Collaborate closely with analog/mixed-signal designers on SerDes AFE integration
- →Own design deliverables and milestones from RTL development through tapeout signoff
- →Define and implement auto-negotiation, link training, and PHY initialization state machines
- →Develop power-efficient digital architectures for data center and AI/ML interconnect applications
- →Participate in standards bodies and stay current with emerging 224G/448G specifications
- →Design firmware-accessible register interfaces and configuration/calibration logic
- →Support post-silicon characterization and debug activities
Requirements
- ✓Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
- ✓12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs
- ✓Strong RTL design skills in SystemVerilog with deep understanding of synthesis and timing closure
- ✓Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls
- ✓Strong working knowledge of IEEE 802.3 and OIF CEI specifications
- ✓Hands-on experience with high-speed digital design on advanced process nodes
- ✓Experience working at the digital-analog boundary including specification of DAC/ADC interfaces
- ✓Demonstrated technical leadership with ability to mentor engineers and deliver silicon on aggressive schedules
- ✓Experience with optical/electrical interconnects, chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus
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